`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:10:00 04/24/2014 
// Design Name: 
// Module Name:    Interface 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Interface(sigO, sigI, sys_CLK);
	output	[2:0]	sigO;
	input		[2:0]	sigI;
	input				sys_CLK;
	 
	reg		[2:0]	sigO;
	reg  		[23:0] counter4Hz;

	always @(posedge sys_CLK) begin        //4Hz??
		if(counter4Hz==1562500) begin //
			if(sigI!=3'b0) begin
				counter4Hz=0;
				sigO=sigI;
			end
			else
				sigO=3'b0;
		end
		else begin
         counter4Hz=counter4Hz+24'b1;
		end
	end
	
endmodule
